Download Verilog FAQ PDF

TitleVerilog FAQ
TagsHardware Description Language Digital Electronics Computer Engineering Computing Technology
File Size399.2 KB
Total Pages31
Table of Contents
                            Verilog FAQ
VCD (Value Change Data)
Different types of Verilog Simulators
                        
Document Text Contents
Page 1

Verilog FAQ

What is VCD and is there any free tool to view it ?

VCD - Value Change Dump format - is an ASCII file that contains the "Changes in
Values of Signals". This is a STANDARD format and is compatible between different
waveform viewers etc. Also most of the simulators can write out VCD files - both VHDL
& Verilog, though in Verilog you could do it more easily (than in VHDL - where you
have to go through your simulator's C-API) with the system tasks like $dumpvars.

VCD (Value Change Data)
Verilog simulator dumps the simulation information for waveform viewing in VCD
Format (Value Change Data).

Different types of Verilog Simulators

There are mainly two types of simulators available.

Event Driven
Cycle Based

Event-based Simulator:

This Digital Logic Simulation method sacrifices performance for rich functionality:
every active signal is calculated for every device it propagates through during a
clock cycle. Full Event-based simulators support 4-28 states; simulation of
Behavioral HDL, RTL HDL, gate, and transistor representations; full timing
calculations for all devices; and the full HDL standard. Event-based simulators
are like a Swiss Army knife with many different features but none are particularly
fast.

Event based simulators are further categorized in 2 types.

Compiled-Code Simulators:

This technique takes the input definition (HDL) of the design and spends time
compiling it into a new data structure in order to enable much faster calculations
during run-time. You sacrifice compile time to be able to run large numbers of
tests faster. it is used in some high end, Event-based simulators.

e.g. Synopsys Inc.'s VCS Simulator converts verilog files into C code which then
be compiled and run, just like any other executable file. It is 10 to 50 times faster
than any other interpretive simulator.
see http://www.synopsys.com/products/simulation/vcs_ds.html

http://www.synopsys.com/index.html/products/simulation/vcs_ds.html

Page 2

Cadence's Native Compiled Verilog generates direct machine language
instructions from verilog files.
see http://www.cadence.com/datasheets/affirma_nc_verilog_sim.html


Interpreted Code Simulators:

This method of simulation allows for rapid change of the source HDL of the
design and restart of the simulation since there is little or no compilation involved
after every design change. This is good for interaction but leads to poor run
times of large tests compared to Compiled Code Techniques.

e.g. Cadence Design Systems Verilog - XL.

see http://www.cadence.com/technology/pcb/products/prev_ds/verilog-xl-
family.html


Cycle Based Simulator:

This is a Digital Logic Simulation method that eliminates unnecessary
calculations to achieve huge performance gains in verifying Boolean logic:

1.) Results are only examined at the end of every clock cycle; and

2.) The digital logic is the only part of the design simulated (no timing
calculations). By limiting the calculations, Cycle based Simulators can provide
huge increases in performance over conventional Event-based simulators.

Cycle based simulators are more like a high speed electric carving knife in
comparison because they focus on a subset of the biggest problem: logic
verification.

Cycle based simulators are almost invariably used along with Static Timing
verifier to compensate for the lost timing information coverage.

In following table differences between Event based and Cycle based simulation
are summarized.

Event based Simulation Cycle Based Simulation
Evaluates inputs looking for state
change

Evaluate entire design every clock cycle

Schedule events in time No event scheduling
Calculate time delay No delay calculations or timing checks
Store state values and time No such storage. Very fast, very efficient

http://www.cadence.com/datasheets/affirma_nc_verilog_sim.html
http://www.cadence.com/datasheets/affirma_nc_verilog_sim.html
http://www.cadence.com/datasheets/affirma_nc_verilog_sim.html

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