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TitlePrecision Instrumentation Amplifiers and Read-Out Integrated Circuits
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LanguageEnglish
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Total Pages198
Table of Contents
                            Precision InstrumentationAmplifiers and Read-OutIntegrated Circuits
	Preface
	Contents
	1 Introduction
		1.1…Motivation
		1.2…Overview of Read-Out Electronics for Sensors
		1.3…Instrumentation Amplifier Topologies
			1.3.1 Three-Opamp Topology
			1.3.2 Switched-Capacitor Topology
			1.3.3 Capacitively-Coupled Topology
			1.3.4 Current-Mode Topology
			1.3.5 Current-Feedback Topology
		1.4…Current-Feedback Instrumentation Amplifier
		1.5…Read-Out ICs
		1.6…Targeted Sensor Applications and Challenges
		1.7…Organization of the Thesis
		References
	2 Dynamic Offset Cancellation Techniques for Operational Amplifiers
		2.1…Introduction
		2.2…Low Frequency Errors
			2.2.1 Offset
			2.2.2 1/f Noise
			2.2.3 Drift
		2.3…Dynamic OffsetOffset Cancellation Techniques
			2.3.1 Auto-Zeroing
				2.3.1.1 Output Offset OffsetStorage
				2.3.1.2 Input Offset OffsetStorage
				2.3.1.3 Closed-Loop OffsetOffset Cancellation with Auxiliary Amplifier
				2.3.1.4 Noise in Auto-Zeroing
			2.3.2 Chopping
			2.3.3 Conclusions
		2.4…Charge Injection charge injectionCompensation Techniques in Auto-Zeroed and Chopper Amplifiers
			2.4.1 Compensation Techniques for Charge Injectioncharge injection
			2.4.2 Charge Injection Charge Injectionand Clock Feed-Throughclock feed-through in Chopper Amplifiers
			2.4.3 Chopper Charge Injection Suppression Techniques
			2.4.4 Conclusions
		2.5…Dynamic Offset Compensated Operational Amplifiers
			2.5.1 Feedback
			2.5.2 Ping-Pong Operational Amplifier
			2.5.3 Chopper-CDS Operational Amplifier
			2.5.4 Offset-Stabilized Operational Amplifiers
			2.5.5 Chopper Offset-Stabilized Operational Amplifiers
				2.5.5.1 Continuous-TimeContinuous-Time Integrator
				2.5.5.2 Sample-and-Hold Notch Filter
				2.5.5.3 Continuous-Time continuous-timeNotch Filter
				2.5.5.4 Auto-Correction Feedback Loop
		2.6…Conclusions
		References
	3 Current-Feedback Instrumentation Amplifiers and Gain Accuracy Improvement Techniques
		3.1…Current-Feedback Instrumentation Amplifier
			3.1.1 Indirect Current-Feedback Instrumentation Amplifier
			3.1.2 Direct Current-Feedback Instrumentation Amplifier
		3.2…Precision Current-Feedback Instrumentation Amplifiers
			3.2.1 Chopper-Stabilized Current-Feedback Instrumentation Amplifier
			3.2.2 Ping-Pong Auto-Zeroed Current-Feedback Instrumentation Amplifier
			3.2.3 Conclusions
		3.3…Gain Accuracy Improvement Techniques
			3.3.1 Current-Feedback Instrumentation Amplifier with Resistor-Degenerated Input Stages
			3.3.2 Chopper-Stabilized Current-Feedback Instrumentation Amplifier with Auto-Gain Calibration
			3.3.3 Ping-Pong-Pang Current-Feedback Instrumentation Amplifier
			3.3.4 Conclusions
		References
	4 A Chopper Instrumentation Amplifier with Offset Reduction Loop
		4.1…Amplifier Requirements
		4.2…Amplifier Architecture
		4.3…Offset Reduction Loop
			4.3.1 Basic Concept
			4.3.2 Transfer Function Analysis
		4.4…Other Sources of Chopper Ripple
			4.4.1 Cascode Buffer Isolation
			4.4.2 Chopper Ripple from the Intermediate Stage
		4.5…Applying ORL to General Purpose Instrumentation Amplifiers and Operational Amplifiers
		4.6…Circuit Implementations
			4.6.1 The Input Stages
			4.6.2 The Intermediate and Output Stages
			4.6.3 The Cascode Buffers
			4.6.4 Constant-Gm Bias Circuit
			4.6.5 Chopper Clock Design and Layout
		4.7…Measurement Results
		4.8…Benchmark and Conclusions
		References
	5 A Chopper Instrumentation Amplifier with Gain Error Reduction Loop
		5.1…Motivation
		5.2…Dynamic Element Matching
		5.3…Analog Gain Error Reduction Loop
			5.3.1 Basic Concept
			5.3.2 Qualitative Analysis
			5.3.3 Quantitative Analysis
		5.4…Digitally-Assisted Gain Error Reduction Loop
		5.5…Comparison Between ORL and GERL
		5.6…The Effects of Chopping, DEM and GERL on CFIA Performance
		5.7…Circuit Implementations
			5.7.1 Current-Feedback Instrumentation Amplifier with Analog Gain Error Reduction Loop
				5.7.1.1 Design Considerations and Implementation of DEM
				5.7.1.2 Implementation of the Input and Feedback Gm Stages
				5.7.1.3 Polarity Control Quantizer Q1 in Analog GERL
			5.7.2 Current-Feedback Instrumentation Amplifier with Digitally-Assisted Gain Error Reduction Loop
				5.7.2.1 10-bit Delta Sigma DAC Implementation
				5.7.2.2 Polarity Control Quantizer Q2 in Digitally-Assisted GERL
		5.8…Measurement Results
			5.8.1 Noise
			5.8.2 Output Ripple Measurement
			5.8.3 INLINL
			5.8.4 Gain Accuracy and Gain Drift
			5.8.5 Settling Behavior of Analog GERL and Digitally-Assisted GERL
		5.9…Benchmark and Conclusions
		References
	6 Read-Out Integrated Circuits
		6.1…ADC Requirements
		6.2…Architecture Design of the ADC
			6.2.1 Modulator Topology
			6.2.2 Non-Idealities in the Delta Sigma Modulator
		6.3…Gain Accuracy Improvement Techniques in the Read-Out IC
			6.3.1 Dynamic Element Matching
			6.3.2 Digitally-Assisted Gain Error Correction Scheme
		6.4…Offset and 1/f Noise Suppression Techniques in the Read-Out IC
			6.4.1 Previous Approach (Multi-Stage Chopping and System-Level Chopping)
			6.4.2 Proposed Approach (Input-Stage Chopping Combined with System-Level Chopping)
		6.5…Error Correction Techniques Summary
		6.6…Circuit Implementations
			6.6.1 CFIA Implementation
			6.6.2 ADC Implementation
		6.7…Measurement Results
		6.8…Conclusions
		References
	7 Conclusions
		7.1…Original Contributions
		7.2…Chapter 4
		7.3…Chapter 5
		7.4…Chapter 6
		7.5…Main Findings
		7.6…Other Applications of this Work
		7.7…Future Work
		References
	Summary
	About the Author
	Index
                        
Document Text Contents
Page 1

Analog Circuits and Signal Processing

Series Editors

Mohammed Ismail
Mohamad Sawan

For further volumes:
http://www.springer.com/series/7381

http://www.springer.com/series/7381

Page 2

Rong Wu
Johan H. Huijsing
Kofi A. A. Makinwa

Precision Instrumentation
Amplifiers and Read-Out
Integrated Circuits

123

Page 99

ffiffiffiffiffiffiffiffiffiffiffi

I15
ðW

L
Þ15

s

þ
ffiffiffiffiffiffiffiffiffiffiffi

I16
ðW

L
Þ16

s

¼
ffiffiffiffiffiffiffiffiffi

I5
ðW

L
Þ5

s

þ
ffiffiffiffiffiffiffiffiffiffiffi

I23
ðW

L
Þ23

s

: ð4:23Þ

To maintain the same current-to-dimension ratio expressed by (4.23), the
transistors within the translinear loops are all well-matched in the layout.

With I16 ¼ I5 and ðWL Þ16 ¼ ð
W
L
Þ5 from (4.23), we can get

I23 ¼
ðWL Þ23
ðW

L
Þ15
� I15: ð4:24Þ

To achieve better settling, the demodulation choppers CH51 and CH52 should be
located at the non-dominant poles of the intermediate stage. Therefore, chopper
CH51 was located at the ‘‘quiet’’ sources of the cascode transistors M3 and M4. The
same applies to chopper CH52. Since the thermal noise of the intermediate stage is
suppressed by the gain of the input stage, the differential pair consisting of M1 and
M2 was biased at only 4 lA, resulting in a Gm of 20 lA/V. The unchopped
cascode transistors M3, M4, M34, and M36 are the main source of residual 1/f noise.
However, this is suppressed by the gain of the preceding stages.

4.6.3 The Cascode Buffers

Figure 4.23 shows a schematic diagram of the cascode buffers. Transistors M23
and M24 serve as current buffer 2 (CB2) to avoid chopping the large compensation
voltage across Cint (around 200 mV). Transistors M25 and M26 act as current buffer
1 (CB1) to isolate the chopper CH6 from the sensing capacitors C41 and C42. This
isolation scheme (seen Fig. 4.18), provides lower capacitances Cpar1 and Cpar2
(compared to C41 and C42) at the right side of CH6, so as to reduce the ripple
caused by CB2’s offset.

The ripple reduction ratio is determined by the DC loop gain of the ORL, as
discussed in Sect. 4.3. A DC gain of 120 dB is required in the cascode buffer.
Therefore, a gain-boosting topology was employed to increase its output impedance
(Fig. 4.23a).

The offset of the booster GBn is chopped by CH6, resulting in a square-wave
voltage appearing across the drains of M25 and M26. This voltage charges and
discharges the parasitic capacitors Cpar1,2, creating an AC offset current IAC1.
Furthermore, this square wave voltage modulates the bottom NMOS current
sources to another AC offset current IAC2 [10]. The sum of these two AC currents
charges and discharges the sensing capacitor C41 and C52, appearing as another
source of ripple at the amplifier output. The same goes for GBp, the offset of which
has a similar effect.

To suppress this ripple, the position of the chopper was modified (Fig. 4.23b) so
that these drain capacitances are located at the virtual grounds established by the
gain-boosting amplifiers [10]. Now the mismatch of the bottom current sources

4.6 Circuit Implementations 91

Page 100

and the offset of GBn appear as a square wave at nodes 1 and 2 (Fig. 4.23b). This
square voltage charges and discharges Cpar3,4, generating an AC current. To reduce
this AC current, both CH6 and M23, M24 were implemented with minimum-size
devices. Therefore, the residual ripple caused by the offset of GBn and the mis-
match of the bottom current sources is filtered out by the integration capacitor Cint.
The AC current due to the offset of the upper current sources and GBp is mitigated
in the same manner.

Compensation Gm Stage Gm5
To minimize the noise contribution from the ORL and increase the input range

of the compensation stage Gm5 in Fig. 4.18, Gm5 is implemented with a resistor-
degenerated PMOS differential pair, as shown in Fig. 4.24. Its transconductance is
14 lA/V, which is 1/18 of the input stage Gm3.

R1 R2

Vin-

Vin+
IORL+
I

Fig. 4.24 Block diagram of
the weak Gm stage Gm5

- +
-+

- +
-+

- +
-+

- +
-+

M23 M24

M25 M26

M23

M25 M26

CH7

CH8

CH9

R1 R2
GNDA

VDDAVDDA

GBp

GBnGBn

GBp

Int+ Int-

CH 9

CH6

GNDA
R1 R2

3 4 3 4

Cascode buffer 1

Cascode buffer 2

1 2

Vos,Gn

Vos,Gp

VB

Vos,Gn

Vos,Gp

C41

C42

Cint Cint

iAC

Cpar2
Cpar1

Vout+

Vout-

Vout+

Vout-

CH 6

Int+ Int-

VB
C41

C42

1 2

Cpar3 Cpar4

(a) (b)

M27 M28 M27 M28

M24

Fig. 4.23 Implementation of the gain-boosted cascode buffer

92 4 A Chopper Instrumentation Amplifier with Offset Reduction Loop

Page 197

F
Feedback, 164, 169, 171, 176, 177, 179
Feed-forward, 141–143, 165, 166

G
Gain accuracy, 9, 10, 14, 16–18, 41, 51
Gain drift, 11, 14, 15, 174, 177
Gain error, 4, 6, 10, 70, 74, 117
Gain error reduction loop, 10, 18, 109, 114,

118, 180
General purpose, 16, 38, 69, 70, 84,

104, 181
Ground-sensing, 59
Guard band, 36
guard time, 36, 37

H
Hall sensors, 1–3, 16

I
Impedance balancing, 162, 170, 172, 177, 180,

182, 186
Incremental, 12, 13, 138, 140, 141
INL, 117, 118, 129, 131, 148, 171, 174
Input impedance, 3, 6, 7, 32, 51, 176
Input offset current, 33
Input bias current, 34, 35, 47
Integrator leakage, 145–147
Instrumentation amplifier, 3–5, 9, 11, 15, 51,

52, 54, 69, 102, 107, 137, 169, 171,
176, 181

K
kT/C noise, 6, 145

L
Linear interpolation, 153, 177, 180
Linearity, 5, 8, 12, 14, 51, 136, 138, 148
Loop-gain, 144
Low-pass, 28, 36, 76, 79, 112, 125, 153
Low-threshold, 88, 89, 98, 122, 127,

160, 181
Low-threshold cascode, 88, 89, 122, 181

M
Modulation, 21, 28, 29, 40, 71, 93, 116, 119,

160, 181
Multiplexer, 108, 153

Multiplicative, 110, 116
Multi-stage chopping, 138, 155, 168, 170, 176,

179, 180

N
Nested-chopping, 155, 156
Noise folding, 6, 12, 18, 27, 29, 46, 71
Noise-shaping, 11
Nonlinearity compensation
Notch filter, 42, 44–47, 74, 76, 102, 180

O
Offset, 4, 7, 10, 14, 21, 70, 104,

156, 182
Offset gain error, 14
Offset reduction loop, 10, 18, 74, 102,

176, 182
Operational amplifier, 4, 5, 16, 17, 21, 24, 38,

40, 41, 44–47, 55, 56, 69, 181
Output impedance, 88, 160–162, 181

P
Periodic noise analysis (PNOISE), 72, 158
Periodic steady-state (PSS), 72, 147, 158
Phase shift, 45–47, 74, 79, 80, 103, 112,

180, 184
Phase shift comparator, 45
Ping-pong, 21, 37, 66, 135
Ping-pong-pang, 62, 66
Power efficient, 5, 9, 42, 153, 159
PSRR, 15, 70, 103, 132, 134

R
Ratio-metric, 139, 148, 177
Read-out IC, 174, 180, 182
Resistor-degenerated (degeneration), 59, 65,

107, 135, 163, 170
Resistor-degeneration, 10, 17, 66, 135
Ripple reduction, 21, 74, 80, 103, 179

S
Sample and hold, 7, 42, 44
Self-heating, 4, 16, 70
Sensor, 1, 2, 7, 16, 137
Settling, 27, 46, 116, 150, 166
Signal-dependent, 54, 65, 66, 113, 135,

165, 180
Sinc2 filter
Sinc3 filter, 174

192 Index

Page 198

Start-up, 74, 116, 133, 153, 155
Strain gauge, 2, 3, 16, 107, 137
Swapper, 108, 112, 117, 152
Switched-capacitor, 5, 74, 80, 145
Synchronous demodulator

(demodulation), 76
System-level chopping, 13, 137, 148, 158, 176

T
Temperature drift, 14, 23, 66, 109, 135, 153,

174
Thermistor bridge, 1, 16, 174
Thermocouple, 2, 4, 16, 23, 137
Three-opamp, 5, 91
Trimming, 10, 21, 113, 135, 177, 180

Index 193

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