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Titlepipelining
TagsDigital Electronics Electronic Engineering Central Processing Unit Instruction Set Integrated Circuit
File Size1.2 MB
Total Pages75
Table of Contents
                            What is pipelining?
Instruction Pipelining (1/2)
Instruction Pipelining (2/2)
Pipelining Example: Laundry
Sequential Laundry
Pipelined Laundry Start work ASAP
Pipelining Lessons
Slide 8
Slide 9
CPU Pipelining
CPU Pipelining
Slide 12
CPU Pipelining: Example
Slide 14
Slide 15
MIP dataflow
CPU Pipelining Datapath resources
CPU Pipelining Example: (1/2)
CPU Pipelining Example: (2/2)
Pipelining MIPS Instruction Set
CPU Pipelining:MIPS  Fast Fetch and Decode
Slide 22
CPU Pipelining:MIPS  Fast Decode
Slide 24
CPU Pipelining:MIPS Fast Execution
Slide 26
CPU Pipelining:MIPS  Fast Execution
Instruction Pipelining Review
MIPS In-Order Single-Issue Integer Pipeline Ideal Operation
Slide 30
A Pipelined MIPS Integer Datapath
Pipelining Performance Example
Pipeline Hazards
How do we deal with hazards?
Stalls and performance
Structural Hazards
An example of a structural hazard
How is it resolved?
Or alternatively…
Remember the common case!
Data Hazards
Slide 42
Minimizing Data hazard Stalls by Forwarding
Slide 44
Slide 45
Data Hazard Classification
Data Hazard Classification
Read after write (RAW) hazards
Write after write (WAW) hazards
Write after read (WAR) hazards
Data Hazards Requiring Stall Cycles
Slide 52
Hardware Pipeline Interlocks
Slide 54
Data hazards and the compiler
Some example situations
Detecting Data Hazards
Static Compiler Instruction Scheduling (Re-Ordering)  for Data Hazard Stall Reduction
Static Compiler Instruction Scheduling Example
Antidependence
Control Hazards
Reducing Branch Stall Cycles
Slide 63
Compile-Time Reduction of Branch Penalties
Slide 65
Static Compiler Branch Prediction
Slide 67
Dynamic branch prediction
Branch target buffer
Reduction of Branch Penalties: Delayed Branch
Delayed Branch Example
Delayed Branch-delay Slot Scheduling Strategies
Pipeline Performance Example
Pipelining Summary
Slide 75
                        
Document Text Contents
Page 1

August 4, 2011204521 Digital System
Architecture

1

What is pipelining?

Implementation technique in which multiple
instructions are overlapped in execution

Real-life pipelining examples?
– Laundry

– Factory production lines
– Traffic??

Page 2

August 4, 2011204521 Digital System
Architecture

2

Instruction Pipelining (1/2)
Instruction pipelining is CPU implementation technique

where multiple operations on a number of instructions are
overlapped.

An instruction execution pipeline involves a number of
steps, where each step completes a part of an

instruction. Each step is called a pipeline stage or a
pipeline segment.

The stages or steps are connected in a linear fashion:
one stage to the next to form the pipeline -- instructions
enter at one end and progress through the stages and

exit at the other end.
The time to move an instruction one step down the

pipeline is is equal to the machine cycle and is
determined by the stage with the longest processing

delay.

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August 4, 2011204521 Digital System
Architecture

37

An example of a structural hazard

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RegMem DM Reg

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RegMem DM Reg

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RegMem DM Reg

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RegMem DM Reg

Time

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RegMem DM Reg

Load

Instruction 1

Instruction 2

Instruction 3

Instruction 4

What’s the problem here?

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August 4, 2011204521 Digital System
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How is it resolved?

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RegMem DM Reg

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Time

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RegMem DM Reg

Load

Instruction 1

Instruction 2

Stall

Instruction 3

Bubble Bubble Bubble Bubble Bubble

Pipeline generally stalled by
inserting a “bubble” or NOP

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August 4, 2011204521 Digital System
Architecture

Pipelining Summary

Pipelining overlaps the execution of multiple instructions.

With an idea pipeline, the CPI is one, and the speedup is
equal to the number of stages in the pipeline.

However, several factors prevent us from achieving the
ideal speedup, including

– Not being able to divide the pipeline evenly
– The time needed to empty and flush the pipeline

– Overhead needed for pipelining
– Structural, data, and control hazards

Just overlap tasks, and easy if tasks are independent

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August 4, 2011204521 Digital System
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Pipelining Summary

Speed Up VS. Pipeline Depth; if ideal CPI is 1, then:

Hazards limit performance
– Structural: need more HW resources
– Data: need forwarding, compiler scheduling
– Control: early evaluation & PC, delayed branch, prediction

Increasing length of pipe increases impact of hazards;
pipelining helps instruction bandwidth, not latency

Compilers reduce cost of data and control hazards
– Load delay slots
– Branch delay slots
– Branch prediction

Speedup =
Pipeline Depth

1 + Pipeline stall CPI
X

Clock Cycle Unpipelined

Clock Cycle Pipelined

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