Document Text Contents
Page 1
Digital Systems
Principles and Applications
Ronald J. Tocci
Monroe Community College
Neal S. Widmer
Purdue University
Gregory L. Moss
Purdue University
TENTH EDITION
Pearson Education International
TOCCMF01_0131739697.QXD 12/22/2005 09:09 PM Page iii
Page 2
If you purchased this book within the United States or Canada you should be aware that
it has been wrongfully imported without the approval of the Publisher or the Author.
Director of Development: Vern Anthony
Editorial Assistant: Lara Dimmick
Production Editor: Stephen C. Robb
Production Coordination: Peggy Hood, TechBooks/GTS
Design Coordinator: Diane Y. Ernsberger
Cover Designer: Jason Moore
Cover Art: Getty One
Production Manager: Matt Ottenweller
Marketing Manager: Ben Leonard
This book was set in TimesEuropa Roman by TechBooks/GTS York, PA Campus. It was
printed and bound by Courier Kendallville, Inc. The cover was printed by Phoenix
Color Corp.
MultiSIM® is a trademark of Electronics Workbench.
Altera is a trademark and service mark of Altera Corporation in the United States and
other countries. Altera products are the intellectual property of Altera Corporation and
are protected by copyright laws and one or more U.S. and foreign patents and patent ap-
plications.
Copyright © 2007 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458.
Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This
publication is protected by Copyright and permission should be obtained from the pub-
lisher prior to any prohibited reproduction, storage in a retrieval system, or transmission
in any form or by any means, electronic, mechanical, photocopying, recording, or likewise.
For information regarding permission(s), write to: Rights and Permissions Department.
Pearson Prentice Hall™ is a trademark of Pearson Education, Inc.
Pearson® is a registered trademark of Pearson plc
Prentice Hall® is a registered trademark of Pearson Education, Inc.
Pearson Education Ltd. Pearson Education Australia Pty. Limited
Pearson Education Singapore, Pte. Ltd. Pearson Education North Asia Ltd.
Pearson Education Canada, Ltd. Pearson Educación de Mexico, S.A. de C.V.
Pearson Education—Japan Pearson Education Malaysia, Pte. Ltd.
Pearson Education, Upper Saddle River,
New Jersey
10 9 8 7 6 5 4 3 2 1
ISBN: 0-13-173969-7
TOCCMF01_0131739697.QXD 12/23/05 1:45 AM Page iv
Page 485
performed on each rising edge of the clock. To implement a shift register, we
can use structural code to describe a string of flip-flops. Making the shift reg-
ister versatile by allowing it to shift right or left or to parallel load would
make this file quite long and thus hard to read and understand using struc-
tural methods. A much better approach is to use the more abstract and intu-
itive methods available in HDL to describe the circuit concisely. To do this,
we must develop a strategy that will create the shifting action. The concept
is very similar to the one presented in Example 7-16, where a D flip-flop reg-
ister chip (74174) was wired to form a shift register. Rather than thinking of
the shift register as a serial string of flip-flops, we consider it as a parallel
register whose contents are being transferred in parallel to a set of bits that
is offset by one bit position. Figure 7-76 demonstrates the concept of each
transfer needed in this design.
Solution
A very reasonable first step is to define a two-bit input named mode with
which we can specify mode 0, 1, 2, or 3.The next challenge is deciding how to
choose among the four operations using HDL. Several methods can work
here. The CASE structure was chosen because it allows us to choose a differ-
ent set of HDL statements for each and every possible mode value. There is
no priority associated with checking for the existing mode settings or over-
lapping ranges of mode numbers, so we do not need the advantages of the
IF/ELSE construct.The HDL solutions are given in Figures 7-83 and 7-84.The
same inputs and outputs are defined in each approach: a clock, four bits of
parallel load data, a single bit for the serial input to the register, two bits for
the mode selection, and four output bits.
SECTION 7-22/HDL REGISTERS 457
FIGURE 7-83 AHDL universal shift register.
1 SUBDESIGN fig7_83
2 (
3 clock :INPUT;
4 din[3..0] :INPUT; -- parallel data in
5 ser_in :INPUT; -- serial data in from Left or Right
6 mode [1..0] :INPUT; -- MODE Select: 0=hold, 1=right, 2=left, 3=load
7 q[3..0] :OUTPUT;
8 )
9 VARIABLE
10 ff[3..0] :DFF; -- define register set
11 BEGIN
12 ff[].clk = clock; -- synchronous clock
13 CASE mode[] IS
14 WHEN 0 => ff[].d = ff[].q; -- hold shift
15 WHEN 1 => ff[2..0].d = ff[3..1].q); -- shift right
16 ff[3].d = ser_in; -- new data from left
17 WHEN 2 => ff[3..1].d = ff[2..0].q; -- shift left
18 ff[0].d = ser_in; -- new data bit from right
19 WHEN 3 => ff[].d = din[]; -- parallel load
20 END CASE;
21 q[] = ff[]; -- update outputs
22 END;
TOCCMC07_0131725793.QXD 12/12/2005 10:50 PM Page 457
Page 486
A
H
D
L AHDL SOLUTION
The AHDL solution of Figure 7-83 uses a register of D flip-flops declared by
the name ff on line 10, representing the current state of the register. Because
the flip-flops all need to be clocked at the same time (synchronously), all the
clock inputs are assigned to clock on line 12. The CASE construct selects a
different transfer configuration for each value of the mode inputs. Mode 0
(hold data) uses a direct parallel transfer from the current state to the same
bit positions on the D inputs to produce the identical NEXT state. Mode 1
(shift right), which is described on lines 15 and 16, transfers bits 3, 2, and 1
to bit positions 2, 1, and 0, respectively, and loads bit 3 from the serial input.
Mode 2 (shift left) performs a similar operation in the opposite direction
(see lines 17 and 18). Mode 3 (parallel load) transfers the value on the par-
allel data inputs to become the NEXT state of the register. The code creates
the circuitry that chooses one of these logical operations on the actual regis-
ter, and the proper data is transferred to the output pins on the next clock.
This code can be shortened by combining lines 15 and 16 into a single state-
ment that concatenates the ser_in with the three data bits and groups them
as a set of four bits. The statement that can replace lines 15 and 16 is:
WHEN 1 �> ff[].d � (ser_in, ff[3..1].q);
Lines 17 and 18 can also be replaced by:
WHEN 2 �> ff[].d � (ff[2..0].q,ser_in);
458 CHAPTER 7/COUNTERS AND REGISTERS
ENTITY fig7_84 IS
PORT (
clock :IN BIT;
din :IN BIT_VECTOR (3 DOWNTO 0); -- parallel data in
ser_in :IN BIT; -- serial data in L or R
mode :IN INTEGER RANGE 0 TO 3; -- 0=hold 1=rt 2=lt 3=load
q :OUT BIT_VECTOR (3 DOWNTO 0));
END fig7_84;
ARCHITECTURE a OF fig7_84 IS
BEGIN
PROCESS (clock) -- respond to clock
VARIABLE ff :BIT_VECTOR (3 DOWNTO 0);
BEGIN
IF (clock'EVENT AND clock = '1') THEN
CASE mode IS
WHEN 0 => ff := ff; -- hold data
WHEN 1 => ff(2 DOWNTO 0) := ff(3 DOWNTO 1); -- shift right
ff(3) := ser_in;
WHEN 2 => ff(3 DOWNTO 1) := ff(2 DOWNTO 0); -- shift left
ff(0) := ser_in;
WHEN 3 => ff := din; -- parallel load
END CASE;
END IF;
q <= ff; -- update outputs
END PROCESS;
END a;
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
FIGURE 7-84 VHDL universal shift register.
TOCCMC07_0131725793.QXD 12/13/05 4:51 AM Page 458
Page 969
x = A + BA
B
OR Gate
A
B
x = AB
x = A ⊕ B
= AB + ABA
B
A
B
x = A ⊕ B = AB + AB
x = AB
A
B
x = A + BA
B
AND Gate
XOR
NOR Gate
NAND Gate
XNOR
LOGIC GATE SYMBOLS
A
0
0
1
1
B
0
1
0
1
0
1
1
1
OR
A + B
NOR
A + B
1
0
0
0
AND
A · B
0
0
0
1
NAND
A · B
1
1
1
0
A ⊕ B
XOR
A ⊕ B
XNOR
0
1
1
0
1
0
0
1
LOGIC GATE TRUTH TABLES
BOOLEAN THEOREMS
1.
4.
7.
10.
13a.
15a.
17.
x · 0 = 0
x · x = 0
x + x = x
x · y = y · x
x(y + z) = xy + xz
x + xy = x + y
xy = x + y
x · 1 = x
x + 0 = x
x + x = 1
x + (y + z) = (x + y) + z = x + y + z
(w + x) (y + z) = wy + xy + wz + xz
x + xy = x + y
x · x = x
x + 1 = 1
x + y = y + x
x(yz) = (xy)z = xyz
x + xy = x
x + y = x y
3.
6.
9.
12.
14.
16.
2.
5.
8.
11.
13b.
15b.
TOCCME01_0131725793.QXD 12/22/2005 09:06 PM Page 2
Page 970
CLEAR
Q
Q
Q
S
C
Q
(Alternate symbol)
SET
Normally
low
S
0
1
0
1
C
0
0
1
1
Q
No change
Q = 1
Q = 0
Invalid
Q
S
C
Q
(Alternate symbol)
CLEAR
Q
Q
SET
Normally
high
S
0
1
0
1
C
0
0
1
1
Q
Invalid
Q = 0
Q = 1
No change
Q
S
CLK
C
Q
S
0
1
0
1
C
0
0
1
1
CLK Q
Q0 (no change)
1
0
Ambiguous
↓ of CLK has no effect on Q
Q
J
CLK
K
Q
J
0
1
0
1
K
0
0
1
1
CLK Q
Q0 (no change)
1
0
Q0 (toggles)
↓ of CLK has no effect on Q
Q
D
CLK
Q
↓ of CLK has no effect on Q
D
0
1
Q
0
1
CLK
⎯Q
D
EN
Q EN
0
1
1
D
X
0
1
Q*
No change
0
1
*Q follows D input
while EN is HIGH
Q
J
CLK
K
Q
CLR
PRE
PRE
1
1
0
0
CLR
1
0
1
0
Q*
No effect; FF can respond to J, K and CLK
Q = 0 independent of J, K, CLK
Q = 1 independent of J, K, CLK
Ambiguous (not used)
*CLK can be in any state
FLIP-FLOPS
NOR Latch
NAND Latch
Clocked J-K
Clocked D
D Latch
Clocked S-C
Asynchronous
Inputs
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
TOCCME01_0131725793.QXD 12/22/2005 09:06 PM Page 3
Digital Systems
Principles and Applications
Ronald J. Tocci
Monroe Community College
Neal S. Widmer
Purdue University
Gregory L. Moss
Purdue University
TENTH EDITION
Pearson Education International
TOCCMF01_0131739697.QXD 12/22/2005 09:09 PM Page iii
Page 2
If you purchased this book within the United States or Canada you should be aware that
it has been wrongfully imported without the approval of the Publisher or the Author.
Director of Development: Vern Anthony
Editorial Assistant: Lara Dimmick
Production Editor: Stephen C. Robb
Production Coordination: Peggy Hood, TechBooks/GTS
Design Coordinator: Diane Y. Ernsberger
Cover Designer: Jason Moore
Cover Art: Getty One
Production Manager: Matt Ottenweller
Marketing Manager: Ben Leonard
This book was set in TimesEuropa Roman by TechBooks/GTS York, PA Campus. It was
printed and bound by Courier Kendallville, Inc. The cover was printed by Phoenix
Color Corp.
MultiSIM® is a trademark of Electronics Workbench.
Altera is a trademark and service mark of Altera Corporation in the United States and
other countries. Altera products are the intellectual property of Altera Corporation and
are protected by copyright laws and one or more U.S. and foreign patents and patent ap-
plications.
Copyright © 2007 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458.
Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This
publication is protected by Copyright and permission should be obtained from the pub-
lisher prior to any prohibited reproduction, storage in a retrieval system, or transmission
in any form or by any means, electronic, mechanical, photocopying, recording, or likewise.
For information regarding permission(s), write to: Rights and Permissions Department.
Pearson Prentice Hall™ is a trademark of Pearson Education, Inc.
Pearson® is a registered trademark of Pearson plc
Prentice Hall® is a registered trademark of Pearson Education, Inc.
Pearson Education Ltd. Pearson Education Australia Pty. Limited
Pearson Education Singapore, Pte. Ltd. Pearson Education North Asia Ltd.
Pearson Education Canada, Ltd. Pearson Educación de Mexico, S.A. de C.V.
Pearson Education—Japan Pearson Education Malaysia, Pte. Ltd.
Pearson Education, Upper Saddle River,
New Jersey
10 9 8 7 6 5 4 3 2 1
ISBN: 0-13-173969-7
TOCCMF01_0131739697.QXD 12/23/05 1:45 AM Page iv
Page 485
performed on each rising edge of the clock. To implement a shift register, we
can use structural code to describe a string of flip-flops. Making the shift reg-
ister versatile by allowing it to shift right or left or to parallel load would
make this file quite long and thus hard to read and understand using struc-
tural methods. A much better approach is to use the more abstract and intu-
itive methods available in HDL to describe the circuit concisely. To do this,
we must develop a strategy that will create the shifting action. The concept
is very similar to the one presented in Example 7-16, where a D flip-flop reg-
ister chip (74174) was wired to form a shift register. Rather than thinking of
the shift register as a serial string of flip-flops, we consider it as a parallel
register whose contents are being transferred in parallel to a set of bits that
is offset by one bit position. Figure 7-76 demonstrates the concept of each
transfer needed in this design.
Solution
A very reasonable first step is to define a two-bit input named mode with
which we can specify mode 0, 1, 2, or 3.The next challenge is deciding how to
choose among the four operations using HDL. Several methods can work
here. The CASE structure was chosen because it allows us to choose a differ-
ent set of HDL statements for each and every possible mode value. There is
no priority associated with checking for the existing mode settings or over-
lapping ranges of mode numbers, so we do not need the advantages of the
IF/ELSE construct.The HDL solutions are given in Figures 7-83 and 7-84.The
same inputs and outputs are defined in each approach: a clock, four bits of
parallel load data, a single bit for the serial input to the register, two bits for
the mode selection, and four output bits.
SECTION 7-22/HDL REGISTERS 457
FIGURE 7-83 AHDL universal shift register.
1 SUBDESIGN fig7_83
2 (
3 clock :INPUT;
4 din[3..0] :INPUT; -- parallel data in
5 ser_in :INPUT; -- serial data in from Left or Right
6 mode [1..0] :INPUT; -- MODE Select: 0=hold, 1=right, 2=left, 3=load
7 q[3..0] :OUTPUT;
8 )
9 VARIABLE
10 ff[3..0] :DFF; -- define register set
11 BEGIN
12 ff[].clk = clock; -- synchronous clock
13 CASE mode[] IS
14 WHEN 0 => ff[].d = ff[].q; -- hold shift
15 WHEN 1 => ff[2..0].d = ff[3..1].q); -- shift right
16 ff[3].d = ser_in; -- new data from left
17 WHEN 2 => ff[3..1].d = ff[2..0].q; -- shift left
18 ff[0].d = ser_in; -- new data bit from right
19 WHEN 3 => ff[].d = din[]; -- parallel load
20 END CASE;
21 q[] = ff[]; -- update outputs
22 END;
TOCCMC07_0131725793.QXD 12/12/2005 10:50 PM Page 457
Page 486
A
H
D
L AHDL SOLUTION
The AHDL solution of Figure 7-83 uses a register of D flip-flops declared by
the name ff on line 10, representing the current state of the register. Because
the flip-flops all need to be clocked at the same time (synchronously), all the
clock inputs are assigned to clock on line 12. The CASE construct selects a
different transfer configuration for each value of the mode inputs. Mode 0
(hold data) uses a direct parallel transfer from the current state to the same
bit positions on the D inputs to produce the identical NEXT state. Mode 1
(shift right), which is described on lines 15 and 16, transfers bits 3, 2, and 1
to bit positions 2, 1, and 0, respectively, and loads bit 3 from the serial input.
Mode 2 (shift left) performs a similar operation in the opposite direction
(see lines 17 and 18). Mode 3 (parallel load) transfers the value on the par-
allel data inputs to become the NEXT state of the register. The code creates
the circuitry that chooses one of these logical operations on the actual regis-
ter, and the proper data is transferred to the output pins on the next clock.
This code can be shortened by combining lines 15 and 16 into a single state-
ment that concatenates the ser_in with the three data bits and groups them
as a set of four bits. The statement that can replace lines 15 and 16 is:
WHEN 1 �> ff[].d � (ser_in, ff[3..1].q);
Lines 17 and 18 can also be replaced by:
WHEN 2 �> ff[].d � (ff[2..0].q,ser_in);
458 CHAPTER 7/COUNTERS AND REGISTERS
ENTITY fig7_84 IS
PORT (
clock :IN BIT;
din :IN BIT_VECTOR (3 DOWNTO 0); -- parallel data in
ser_in :IN BIT; -- serial data in L or R
mode :IN INTEGER RANGE 0 TO 3; -- 0=hold 1=rt 2=lt 3=load
q :OUT BIT_VECTOR (3 DOWNTO 0));
END fig7_84;
ARCHITECTURE a OF fig7_84 IS
BEGIN
PROCESS (clock) -- respond to clock
VARIABLE ff :BIT_VECTOR (3 DOWNTO 0);
BEGIN
IF (clock'EVENT AND clock = '1') THEN
CASE mode IS
WHEN 0 => ff := ff; -- hold data
WHEN 1 => ff(2 DOWNTO 0) := ff(3 DOWNTO 1); -- shift right
ff(3) := ser_in;
WHEN 2 => ff(3 DOWNTO 1) := ff(2 DOWNTO 0); -- shift left
ff(0) := ser_in;
WHEN 3 => ff := din; -- parallel load
END CASE;
END IF;
q <= ff; -- update outputs
END PROCESS;
END a;
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
FIGURE 7-84 VHDL universal shift register.
TOCCMC07_0131725793.QXD 12/13/05 4:51 AM Page 458
Page 969
x = A + BA
B
OR Gate
A
B
x = AB
x = A ⊕ B
= AB + ABA
B
A
B
x = A ⊕ B = AB + AB
x = AB
A
B
x = A + BA
B
AND Gate
XOR
NOR Gate
NAND Gate
XNOR
LOGIC GATE SYMBOLS
A
0
0
1
1
B
0
1
0
1
0
1
1
1
OR
A + B
NOR
A + B
1
0
0
0
AND
A · B
0
0
0
1
NAND
A · B
1
1
1
0
A ⊕ B
XOR
A ⊕ B
XNOR
0
1
1
0
1
0
0
1
LOGIC GATE TRUTH TABLES
BOOLEAN THEOREMS
1.
4.
7.
10.
13a.
15a.
17.
x · 0 = 0
x · x = 0
x + x = x
x · y = y · x
x(y + z) = xy + xz
x + xy = x + y
xy = x + y
x · 1 = x
x + 0 = x
x + x = 1
x + (y + z) = (x + y) + z = x + y + z
(w + x) (y + z) = wy + xy + wz + xz
x + xy = x + y
x · x = x
x + 1 = 1
x + y = y + x
x(yz) = (xy)z = xyz
x + xy = x
x + y = x y
3.
6.
9.
12.
14.
16.
2.
5.
8.
11.
13b.
15b.
TOCCME01_0131725793.QXD 12/22/2005 09:06 PM Page 2
Page 970
CLEAR
Q
Q
Q
S
C
Q
(Alternate symbol)
SET
Normally
low
S
0
1
0
1
C
0
0
1
1
Q
No change
Q = 1
Q = 0
Invalid
Q
S
C
Q
(Alternate symbol)
CLEAR
Q
Q
SET
Normally
high
S
0
1
0
1
C
0
0
1
1
Q
Invalid
Q = 0
Q = 1
No change
Q
S
CLK
C
Q
S
0
1
0
1
C
0
0
1
1
CLK Q
Q0 (no change)
1
0
Ambiguous
↓ of CLK has no effect on Q
Q
J
CLK
K
Q
J
0
1
0
1
K
0
0
1
1
CLK Q
Q0 (no change)
1
0
Q0 (toggles)
↓ of CLK has no effect on Q
Q
D
CLK
Q
↓ of CLK has no effect on Q
D
0
1
Q
0
1
CLK
⎯Q
D
EN
Q EN
0
1
1
D
X
0
1
Q*
No change
0
1
*Q follows D input
while EN is HIGH
Q
J
CLK
K
Q
CLR
PRE
PRE
1
1
0
0
CLR
1
0
1
0
Q*
No effect; FF can respond to J, K and CLK
Q = 0 independent of J, K, CLK
Q = 1 independent of J, K, CLK
Ambiguous (not used)
*CLK can be in any state
FLIP-FLOPS
NOR Latch
NAND Latch
Clocked J-K
Clocked D
D Latch
Clocked S-C
Asynchronous
Inputs
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
TOCCME01_0131725793.QXD 12/22/2005 09:06 PM Page 3
