Download Designing Bipolar Transistor Radio Frequency Integrated Circuits (Artech House Microwave Library) PDF

TitleDesigning Bipolar Transistor Radio Frequency Integrated Circuits (Artech House Microwave Library)
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LanguageEnglish
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Total Pages331
Table of Contents
                            Designing Bipolar Transistor Radio Frequency Integrated Circuits
	Contents
	Acknowledgments
	CHAPTER 1 Introduction
		References
	CHAPTER 2 Applications
		2.1 Cellular/PCS Handsets
		2.2 Cellular/PCS Infrastructure
		2.3 WLANs
		2.4 Bluetooth
		2.5 UWB
		2.6 WiMax
		2.7 Digital TV and Set-Top Boxes
		2.8 Cognitive Radio
		2.9 Spectrum Allocation in the United States (All Frequencies in Megahertz)
		2.10 Physical Layer Standards
		References
	CHAPTER 3 RFIC Architectures
		3.1 I/Q Receivers
		3.2 I/Q Modulators
		3.3 Nonzero IF Receivers
		3.4 Zero IF Receivers
		3.5 Differential versus Single-Ended Topologies
		References
	CHAPTER 4 InGaP/GaAs HBT Fabrication Technology
		4.1 Transistor Structures
		4.2 Device Models
		4.3 Passive Structures, Their Electrical Models, and Layout Design Rules
		4.4 Maximum Electrical Ratings
		4.5 CAD Layout Tools
		References
	CHAPTER 5 SiGe HBT Fabrication Technology
		5.1 SiGe HBT Transistor Structures
		5.2 Transistor Device Models
		5.3 Passive Device Structures and Models
		5.4 Design Rules
		5.5 CAD Layout
		References
	CHAPTER 6 Passive Circuit Design
		6.1 Low-Pass Filters
		6.2 High-Pass Filters
		6.3 Band-Pass Filters
		6.4 Differential Filters
		6.5 Technology and Substrates
		6.6 Splitters/Dividers
		6.7 Phase Shifters and Baluns
		References
	CHAPTER 7 Amplifier Design Basics
		7.1 Matching Techniques
		7.2 Gain Compensation
		7.3 Fano’s Limit
		7.4 Stability
		7.5 Noise Match
		7.6 Differential Amplifiers
		7.7 Cascode Amplifiers
		References
	CHAPTER 8 Low-Noise Amplifier Design
		8.1 Noise Figure Concepts
		8.2 Noise Temperature
		8.3 Front-end Attenuation and LNAs
		8.4 Multistage Noise Figure Contributions
		8.5 Circuit Topologies for Low Noise
		8.6 Design Example 1: Single-Ended PCS LNA
		8.7 Design Example 2: Three-Transistor Hybrid Darlington Differential LNA Using SiGe Technology
		References
	CHAPTER 9 Power Amplifier Design
		9.1 Loadline Concepts
		9.2 Maximum Power and Efficiency
		9.3 Class AB Power Amplifiers
		9.4 Definitions of Nonlinear Performance Metrics
		9.5 Adjacent Channel Power Ratio
		9.6 Error Vector Magnitude
		9.7 Circuit Topologies for PAs
		9.8 Matching Circuit Options
		9.9 Stability
		9.10 Bias Circuits
		9.11 Design Example 3: Wideband Gain Block Darlington Amplifier
		9.12 Design Example 4: Feedback Power Amplifier Design
		References
	CHAPTER 10 Designing Multistage Amplifiers
		10.1 Multistage LNAs
		10.2 Multistage Power Amplifiers
		10.3 Gain and Power Allocations
		10.4 Active Device Sizing
		10.5 Design Example 5: A Differential PCS PA
		Endnote
		References
	CHAPTER 11 Mixer/Modulator Design
		11.1 Mixer Basics
		11.2 Diode Mixers
		11.3 Single-Balanced Active Multiplying Mixers
		11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell)
		11.5 I/Q Mixers
		11.6 I/Q Modulators
		11.7 Design Example 6: Cellular/PCS Downconverting Mixer RFIC
		References
	CHAPTER 12 Frequency Multiplier Design
		12.1 Frequency Doublers
		12.2 Frequency Triplers
		12.3 Frequency Translators
		References
	CHAPTER 13 Voltage-Controlled Oscillator Design
		13.1 Varactor Diode Basics
		13.2 Negative-Resistance Concepts
		13.3 Types of Resonators
		13.4 Feedback Circuit Topologies for Producing Negative Resistance
		13.5 Frequency-Temperature Stability
		13.6 Phase Noise
		13.7 Quadrature Phase-Shifting Networks
		13.8 Ring Oscillators
		13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO
		13.10 Figure of Merit
		13.11 Electronic Tuning and a Differential VCO Topology
		References
	CHAPTER 14 Layout Design Strategies
		14.1 Minimum Area
		14.2 “On-Chip” versus “Off-Chip” Component Decisions
		14.3 Minimizing Parasitics
		14.4 Testability
		14.5 Types of CAD Systems
		14.6 Foundry Comparison
		14.7 Reticle Assembly
	CHAPTER 15 RFIC Economics
		15.1 Levels of Integration
		15.2 Single-Ended versus Differential Topologies
		15.3 Process Technology Choices
		15.4 Area versus Performance Trade-offs
		15.5 Electrical Yield
		15.6 Prototype Costs
		15.7 Production Costs
	Acronyms
	About the Author
	Index
                        
Document Text Contents
Page 2

Designing Bipolar Transistor Radio
Frequency Integrated Circuits

Page 165

In a similar fashion, the dc-blocking capacitor and the bypass capacitor must
have reactance below about 1 ohm at the operating frequency, Fo, which means,

1/2 FoCb < 1 ohm (9.18)

As in the case of the choke inductor, these capacitors may or may not be located
on-chip, depending on their size and how much chip area is occupied by a capacitor
of this size. The final decision is often purely economic.

Now we consider the circuit requirement for base biasing. Referring to
Figure 9.24, we see the simplest of all base-biasing circuits. This circuit is nothing
more than a resistor attached between the transistor’s base and a voltage source. If
the voltage source exceeds the transistor’s turn-on voltage, Vbe, current will flow in
the base-to-emitter junction, biasing the transistor with a base current of

Ibase = (Vdc – Vbe)/Rbase (9.19)

where

Ibase is the RF transistor’s base current.
Vdc is the base supply voltage.
Rbase is the circuit’s resistance.

152 Power Amplifier Design

Figure 9.23 The combination of a choke inductor, a blocking capacitor, and a bypass capacitor
supplies collector bias to a bipolar power amplifier.

Figure 9.24 A simple base-biasing network composed of a resistor, a blocking capacitor, and a dc
voltage supply.

Page 166

Ibase should be set to produce the desired dc collector current, Ic, according to the
relationship

Icollector = × Ibase (9.20)

where

is the transistor’s current gain (about 100 with most RF transistors).
Icollector is the transistor’s saturated collector current.

With this circuit, Vdc acts as a direct controlling element for setting Icollector, which
can be extraordinarily convenient. However, this simple circuit is not very stable
over temperature since Vbe shifts at high and low temperatures causing changes in
Ibase and Icollector. For this reason, more stable base-biasing circuits have been devel-
oped with the intention of overcoming these temperature-drift problems. The sim-
plest of these alternative base-bias circuits, as shown in Figure 9.25, involves the use
of a second resistor, RB1, connected from the base node to ground. In this case, the
series combination of the two resistors forms a voltage divider, which maintains a
more constant voltage at the transistor’s base terminals. This circuit stabilization of
the base voltage will stabilize the base and collector currents over a wide tempera-
ture range. In order to make this circuit work effectively, it is necessary that the cur-
rent flowing through the resistor divider be somewhat greater than the current
flowing into the transistor’s base. Resistor values must be chosen accordingly to
insure that this condition is met. The trade-off here is that lowering the resistor val-
ues improves base voltage stabilization but increases the amplifier’s overall current
consumption. In handheld, battery-powered applications, where the requirements
are sensitive to all sources of current, base bias current can become a problem for
overall current budgets.

A second method for stabilizing base and collector currents is called current
mirror biasing. The schematic diagram showing a current mirror circuit is presented
in Figure 9.26. In current mirror circuits, a second transistor (area = A2), which is
smaller than the RF transistor (area = A1), is configured so that its base-to-emitter
junction is connected from ground to the base-to-emitter junction of the RF transis-

9.10 Bias Circuits 153

Figure 9.25 A slightly more complex base-biasing circuit for stabilizing the transistor’s base cur-
rent and collector current over temperature.

Page 330

schematic diagram, 100
S-parameters, 101

WiMax, 19–20
Wireless local-area networks (WLANs), 16–17

Y
YIG-tuned oscillators (YTOs), 21

in Ku band, 267
magnetic structure, 271
negative-resistance-type circuit, 267
output power simulation, 271

silicon bipolar transistors, 267
Yttrium iron garnet (YIG), 241–42, 262

Z
Zero IF receivers, 37–41

block diagram, 37
defined, 37
disadvantages, 38
effectiveness, 40
See also Receivers

ZigBee, 23

Index 317

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